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Components for Entertainment Electronics
Satellite Sound IF TDA6170X with Wegener Expander
Data Sheet
07.99
Edition 07.99 Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1995. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
Ausgabe 07.99 Herausgegeben von Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1995. Alle Rechte vorbehalten. Wichtige Hinweise! Gewahr fur die Freiheit von Rechten Dritter leisten wir nur fur Bauelemente selbst, nicht fur Anwendungen, Verfahren und fur die in Bauelementen oder Baugruppen realisierten Schaltungen. Mit den Angaben werden die Bauelemente spezifiziert, nicht Eigenschaften zugesichert. Liefermoglichkeiten und technische Anderungen vorbehalten. Fragen uber Technik, Preise und Liefermoglichkeiten richten Sie bitte an den Ihnen nachstgelegenen Vertrieb Halbleiter in Deutschland oder an unsere Landesgesellschaften im Ausland. Bauelemente konnen aufgrund technischer Erfordernisse Gefahrstoffe enthalten. Auskunfte daruber bitten wir unter Angabe des betreffenden Typs ebenfalls uber den Vertrieb Halbleiter einzuholen. Die Siemens AG ist ein Hersteller von CECCqualifizierten Produkten. Verpackung Bitte benutzen Sie die Ihnen bekannten Verwerter. Wir helfen Ihnen auch weiter - wenden Sie sich an Ihren fur Sie zustandigen Vertrieb Halbleiter. Nach Rucksprache nehmen wir Verpackungsmaterial sortiert zuruck. Die Transportkosten mussen Sie tragen. Fur Verpackungsmaterial, das unsortiert an uns zuruckgeliefert wird oder fur das wir keine Rucknahmepflicht haben, mussen wir Ihnen die anfallenden Kosten in Rechnung stellen. Bausteine in lebenserhaltenden Geraten oder Systemen mussen ausdrucklich dafur zugelassen sein! Kritische Bauelemente1 des Bereichs Halbleiter der Siemens AG durfen nur mit ausdrucklicher schriftlicher Genehmigung des Bereichs Halbleiter der Siemens AG in lebenserhaltenden Geraten oder Systemen2 eingesetzt werden. 1 Ein kritisches Bauelement ist ein in einem lebenserhaltenden Gerat oder System eingesetztes Bauelement, bei dessen Ausfall berechtigter Grund zur Annahme besteht, da das lebenserhaltende Gerat oder System ausfallt bzw. dessen Sicherheit oder Wirksamkeit beeintrachtigt wird. 2 Lebenserhaltende Gerate und Systeme sind (a) zur chirurgischen Einpflanzung in den menschlichen Korper gedacht, oder (b) unterstutzen bzw. erhalten das menschliche Leben. Sollten sie ausfallen, besteht berechtigter Grund zur Annahme, da die Gesundheit des Anwenders gefahrdet werden kann.
TDA6170X Revision History:Current Version: 07.99 Previous Version: old Page new Page Subjects (major changes since last revision)
Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Characteristics The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage. Operating Range In the operating range the functions given in the circuit description are fulfilled. For detailed technical information about "Processing Guidelines" and "Quality Assurance" for ICs, see our "Product Overview".
Data Sheet
1 2 3 4 4.1 5 5.1 6 7 8 8.1 8.2 8.3 8.3.1 8.3.2 8.4 8.5 8.6 8.7 9 10 11 12 13 14 15 15.1
TDA6170X
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pinconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Package outline P-DSO-28-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PLL Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Fast I2C-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Logic Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 IF-Muting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Converter Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 IF Limiter with Demodulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Expander Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 AF Switch and Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Application Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 I2C-Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Semiconductor Group
21.7.99
Satellite Sound IF with Wegener Expander
TDA6170X
Data Sheet
BIPOLAR
1
Features
* Fast I2C-bus controlled (max. 400 kHz) * PLL controlled sound IF tuning with 10 kHz stepwidth * Second order high-pass mixer input * IF MUX for 10.7 MHz broad / small IF filters * Two identical high sensitive alignment free FM demodulators * Original Wegener PANDA 1TM expander * Volume control for individual settings * 50 s / 75 s / J17 de-emphasis for main sound reception * Fully ESD protection
P-DSO-28
Package
2
Ordering Information
Type TDA6170X Package P-DSO-28-1 Ordering Code Q67001-A5214
3
General Description
Multistandard satellite sound IF device consisting of a mixer and a voltage controlled oscillator (VCO) as a frequency converter that can be continuously tuned in 10 kHz increments with crystal accuracy by means of a PLL, two FM limiter amplifiers with PLL FM demodulators followed by two Wegener PANDA1TM expanders. The AF signal passes through two switches. Each switch can select the AF sources and the mono / stereo mode the de-emphasis networks together with the two following volume control stages with audio buffers. In front of one FM section an IF multiplexer is used to select the IF bandwidth. The switching functions and settings of the PLL are controlled by an I2C-bus.
3.1 Application * For use in satellite receivers
Semiconductor Group
1
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Data Sheet 4 Pinconfiguration
P-DSO 28-1 XTAL PD GNDD CAS LP1 LP2 EXT1 AF1 AF2 EXT2 DEEMP2 EXP2 CT EXP2 CR EXP2 TC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 SDA SCL VD MIXIN MIXOUT VA IF1 GNDA IF2 IF3 DEEMP1 EXP1 CT EXP1 CR EXP1 TC
TDA6170X
4.1 Package outline P-DSO-28-1
Semiconductor Group
2
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Data Sheet 5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
TDA6170X
Pin Definitions and Functions
Pin No. XTAL PD GNDD CAS LP1 LP2 EXT1 AF1 AF2 EXT2 DEEMP2 EXP2 CT EXP2 CR EXP2 TC EXP1 TC EXP1 CR EXP1 CT DEEMP1 IF3 IF2 GNDA IF1 VA MIXOUT MIXIN VD SCL SDA Symbol Function crystal input for 4 MHz oscillator synthesizer loop-filter I2C-bus and synthesizer ground I2C-bus address selection FM-PLL lowpass capacitor (channel 1) FM-PLL lowpass capacitor (channel 2) external audio input (channel 1) audio output (channel 1) audio output (channel 2) external audio input (channel 2) de-emphasis capacitor (channel 2) expander tracking capacitor (channel 2) expander release capacitor (channel 2) expander time constant (channel 2) expander time constant (channel 1) expander release capacitor (channel 1) expander tracking capacitor (channel 1) de-emphasis capacitor (channel 1) intercarrier input 3 intercarrier input 2 analog ground intercarrier input 1 analog supply voltage (+8V) intercarrier mixer output mixer input I2C-bus and synthesizer supply voltage (+5V) I2C-bus serial clock input I2C-bus serial data input/output
Semiconductor Group
3
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Data Sheet 6 Block Diagram
TDA6170X
Semiconductor Group
4
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Data Sheet 7 Circuit Description
TDA6170X
7.1 General
The sound intermediate frequencies contained in the baseband of a demodulated FM satellite signal can lie between 5 and 9.9 MHz. This band of frequencies is applied rough filtered to the high-pass input of the converter mixer. The purpose of this mixer is to convert the different sound IF`s in the baseband to fixed output frequencies (e.g. 10.7 / 10.72 MHz). These frequencies are then fed by external filters to the three sound IF inputs. The VCO of the mixer can be continuously tuned between 29 and 40 MHz in 20 kHz increments with crystal accuracy by means of a PLL circuit. The settings of the programmable divider and switching of the IF MUX and de-emphasis networks and volume control are done by the I2C-bus. Pin 5 (CAS) offers two switchable chip addresses to enable parallel operation of two devices. All pins are guarded against electrostatic discharge. SCL and SDA include special protective structures to permit continued bus operation when the device is switched off.
7.2 PLL Description
The VCO signal is applied to the PLL input. It passes through a programmable divider (N=1024 to 2047) and then compared with a reference frequency (fREF = 20 kHz in a digital frequency / phase detector. This frequency is derived from a 4 MHz crystal oscillator whose signal is divided by 200. The phase detector has a charge pump push-pull current output. If the negative edge of the divided VCO signal appears before the negative edge of the reference signal, the current source I+ will pulse for the duration of the phase difference. In the reverse case it is the current sink I-. If both signals are in phase, the output has a high impedance and the PLL is locked. The current pulses are filtered by means of an integrator. The pump current can be switched between two values (1 and 5) by software with a control bit 5I. This permits a change in the control response during and after lock-in state.
7.3 Fast I2C-Bus Interface
Information is exchanged between the processor and the sound IF device on an fast asynchronous bidirectional data bus. The timing for this comes from the processor (input SCL), while pin SDA functions as an I/O depending on the direction of the data (open collector; external pull-up resistor). The bus will work with clock frequencies up to 400 kHz. The data from the processor goes to an I2C-bus controller and are put into registers (latches 0 to x) according to their function. When the bus is not busy, both lines are in the marking state (SDA, SCL are high). Each telegram begins with the start condition: SDA goes low while SCL remains high. All further exchanges of information occur when SCL is low and are read by the controller with the positive clock edge. If SDA goes high while the clock is high, the I2C-bus interface recognizes this as a stop condition and thus the end of the telegram. For what follows, refer to the table of logic assignments below. All telegrams are transferred byte for byte, followed by a ninth clock pulse during which the controller pulls the SDA line to low (i.e. acknowledge condition). The first byte consists of seven address bits with which the processor selects the PLL from among several other peripheral devices (chip select). The eighth bit is always low. The first bit of the first or third data byte in the data part of the telegram determines whether a divider ratio or control information for the IF or audio part will follow. In every case the first byte must be followed by a byte of the same data type (or stop condition). When the supply voltage is applied, a power-on reset circuit prevents the PLL from pulling the SDA line to low and thus blocking the bus.
Semiconductor Group
5
21.7.99
Data Sheet
7.3.1 Logic Allocation
Byte Address Byte Progr. Divider Byte 1 Progr. Divider Byte 2 Control Byte 1 Control Byte 2 Control Byte 3 Address Byte 11 0 0 0 1 1 1 0 0 1 0 0 5I VL2 0 N11 N5 Z2 VL1 0 N10 N4 Z1 VL0 Data 0 N9 N3 Z0 VR2 0 N8 N2 X VR1 MA N7 N1 X VR0 R/W N6 N0 X X X 0 0 A A A A A A A A
TDA6170X
Remarks
PVL2 PVL1 PVL0 PVR2 PVR1 PVR0 1 1 0 0 0 0 0 0 1 1 0 1
=H44 =H46
Address Byte 22
1. Chip address (CAS) Pin 5 grounded 2. Chip address (CAS) Pin 5 open
7.3.2
IF-Muting
IF-Source Function IF1 on off on off off off off off IF2 on on off off off off off off IF3 off off off on on on off off expanders are working, audio = stereo expanders are working, audio = mono expanders are working, audio = mono de-emphasis = 50; audio = mono de-emphasis = 75; audio = mono de-emphasis = J17; audio = mono External audio Mute
Control Bits Z2 0 0 0 0 1 1 1 1 Z1 0 0 1 1 0 0 1 1 Z0 0 1 0 1 0 1 0 1
7.4 Converter Mixer
In the converter mixer the sound subcarriers (frequency band approx. 5 to 9.9 MHz) contained in the baseband of the received composite satellite signal are converted to an output frequency of 10.52 MHz and 10.7 MHz for example. The converter consists of a high-pass input filter followed by a double balanced mixer and a low impedance output. The signal of the on chip voltage controlled oscillator (VCO) is applied to the PLL input.
7.5 IF Limiter with Demodulator
The two limiter amplifiers are implemented as balanced five stage, capacitively coupled differential amplifiers. The three inputs are designed as high-pass inputs. The load resistors for the IF filters are connected to ground. The output signals of the limiter amplifiers are fed directly to the internal PLL FM demodulators. The demodulated AF signals are fed to the input of a pre volume control part in front of the expander the deemphasis networks and audio switches.
Semiconductor Group
6
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Data Sheet
7.6 Expander Description
TDA6170X
The demodulated and level controlled audio signals are fed via low-pass filters to the inputs of two identical expander circuits. The IF3 audio signal is also applied in parallel via different de-emphasis networks to the input of the audio switch for broadband mono reception. The expander circuits have the reverse characteristics of the audio compressor of the TV station. A 3 bit pre volume control (control byte 3: PVL2...PVL0 and PVR2...PVR0) for each audio channel enables a correct adjustment of the expander characteristics and allows the possibility to align to the right level for both broadband and smallband sound IF reception.
7.7 AF Switch and Volume Control
The input signals of the AF switch can be derived from the external audio input pair. However, these signals can also be derived from either the different de-emphasis networks or from both expanders. The selection of the output signals from IF1, IF2 or IF3 is done by using the I2C-bus interface. The switches are followed by a volume control section with buffered outputs Ch1 and Ch2. In case of small-band reception the demodulated signals of IF1 and IF2 are processed in both expanders and fed to the switches. So it is possible to select one of each or both in the audio switches for both AF outputs Ch1 and Ch2. In the case of broad-band audio transmission with 50s, 75s or J17 pre-emphasis the IF3 input is active and with the audio switch the demodulated audio signals are selected after the three de-emphasis networks and fed to both AF outputs in mono mode. The 3 bit volume control (control byte 2: VL2...VL0 and VR2...VR0) in front of each AF output enables the same audio level for different FM deviations of several satellite transponders.
Semiconductor Group
7
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Data Sheet 8 Pinning
Pin No. Symbol Equivalent Circuit
TDA6170X
1
XTAL
2
PD
3
GNDD
4
CAS
Semiconductor Group
8
21.7.99
Data Sheet
Pin No. Symbol Equivalent Circuit
TDA6170X
5
LP1
6
LP2
7
EXT1
8
AF1
Semiconductor Group
9
21.7.99
Data Sheet
Pin No. Symbol Equivalent Circuit
TDA6170X
9
AF2
10
EXT2
11
DEEMP2
12
EXP2 CT
Semiconductor Group
10
21.7.99
Data Sheet
Pin No. Symbol Equivalent Circuit
TDA6170X
13
EXP2 CR
14
EXP2 TC
15
EXP1 TC
16
EXP1 CR
Semiconductor Group
11
21.7.99
Data Sheet
Pin No. Symbol Equivalent Circuit
TDA6170X
17
EXP1 CT
18
DEEMP1
19
IF3
20
IF2
Semiconductor Group
12
21.7.99
Data Sheet
Pin No. Symbol Equivalent Circuit
TDA6170X
21
GNDA
22
IF1
23
VA
24
MIXOUT
Semiconductor Group
13
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Data Sheet
Pin No. Symbol Equivalent Circuit
TDA6170X
25
MIXIN
26
VD
27
SDA
28
SCL
Semiconductor Group
14
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Data Sheet 9 Absolute Maximum Ratings
TDA6170X
The maximal ratings may not be exceeded under any circumstances, not even momentary and individual, as permanent damage to the IC will result.
Ambient Temperature under bias: TA=0 to 70C Limit Values Parameter Supply voltage (digital) Supply voltage (analog) Mixer input IF inputs Crystal oscillator SDA; SCL; CAS Junction temperature Storage temperature Thermal resistance ESD-Protection Symbol min VVD VVA VMIXIN VIF VXTAL V Tj Tstg Rth j-a VESD 0 0 -0.3 -0.3 0 -0.3 0 0 max 6 13.2 13.2 1 1.5 6 150 125 75 2 V V V V V V C C K/W kV all pins Unit Test Conditions
All values are referred to ground (pin), unless stated otherwise. All currents are designated according to the source and sink principle, i.e. if the device pin is to be regarded as a sink (the current flows into the stated pin to internal ground), it has a negative sign, and if it is a source (the current flows from Vs across the designated pin), it has a positive sign.
Semiconductor Group
15
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Data Sheet 10 Operating Range
TDA6170X
Within the operational range the IC operates as described in the circuit description. The AC / DC characteristic limits are not guaranteed.
Limit Values Unit min 4.5 7.2 5 10 29 0 max 5.5 13.2 10 12 42 70 V V MHz MHz MHz C Test Conditions
Parameter Supply voltage (digital) Supply voltage (analog) Input frequency range of converter mixer Input frequency range of sound IF amplifier VCO frequency Ambient temperature
Symbol (Name) VVD VVA fMIXIN fIF fVCO TA
Semiconductor Group
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Data Sheet 11 Electrical Characteristics
TDA6170X
AC / DC characteristics involve the spread of values guaranteed in the specified supply voltage and ambient temperature range. Typical characteristics are the median of the production.
Limit Values Parameter Power Supply Current consumption Vdigital Current consumption Vanalog Mixer Mixer input voltage Mixer output current Input impedance Output frequency range Mixer gain Charge pump Phase detector charge current Phase detector charge current repetition time of charge pump pulses VCO Frequency range VCO VCO frequency VCO sensitivity Cyrstal oscillator (4 MHz) crystal oscillator frequency resonance resistance of crystal parallel capacitance of crystal fxtal Rxtal Cxtal 50 4.5 4 60 10 MHz W pF A fVCO fVCO SVCO 29 35.5 -16 43 MHz MHz MHz/V VPD = 2.5V IPD IPD t 32 160 50 250 50 75 360 A A s I 5I VMIXIN(rms) IMIXOUT RMIXIN fMIXOUT GMIX 4 3.5 10 2 10.7 3 11.5 4 6 200 8 mV mA k MHz dB RL = 100 IVD IVA 30 30 40 40 50 50 mA mA Symbol min typ max Unit Test conditions
input current from external source Ii Sound IF Sound IF input resistance Input frequency range RIF fIF
260 10
330
400 11.5
W MHz S/N(A) > 40 dB; fIF = 10.7 MHz; f = 27 kHz; fmod = 1 kHz fIF = 10.7 MHz; VIF = 5 to 100mV; fmod = 30%
Input sensitivity
VIF(rms)
0.3
1
mV
AM rejection
aAM
45
dB
Semiconductor Group
17
21.7.99
Data Sheet
Limit Values Parameter FM PLL demodulators free-running frequency lock range of PLL Expander Pre volume control range Control resolution Low-pass filter response AF Switch and Volume Control Max. external input voltage Volume control range Control resolution Output Buffer Output DC level Output resistance total harmonic distortion signal to noise ratio VAF RAF THD S/N (A) L/R; R/L 80 100 3.6 125 0.01 150 0.2 V W % dB VEXT(rms) V V -1 -12 1.6 0 -14 2 2 1 -16 2.4 V dB dB PV V 2.5 -3.5 0.6 16 3 -3 0.8 20 3.5 -2.5 1 24 dB dB kHz fcco fCCO 10 10.6 11.5 MHz MHz Symbol min typ max Unit
TDA6170X
Test conditions
PVL = 000 PVL = 111
VL = 000 VL = 111
A-weighted VEXT = 500 mVrms Control Byte = 110 VEXT = 2 Vrms f = 1 kHz Control Byte = 110
crosstalk between channels Overall performance
80
dB
0.5 Input voltage VMIXIN 1.5
1
mV
S/N > 40 dB f = 27kHz, Control Byte = 000 S/N > 40 dB f = 50kHz, Control Byte = 011 f = 27kHz, fmod = 1kHz, Control Byte = 000 f = 50kHz, fmod = 1kHz, Control Byte = 011
3
mV
400 Output voltage VAF 400
500
600
mV
500
600
mV
Semiconductor Group
18
21.7.99
Data Sheet
Limit Values Parameter Symbol min typ max Unit
TDA6170X
Test conditions VMIXIN > 2 mV f = 27kHz, fmod = 1kHz, Control Byte = 000 VMIXIN > 2 mV f = 50kHz, fmod = 1kHz, Control Byte = 011 A-weighted, f = 27kHz, fmod = 1kHz, Control Byte = 000 Control Byte = 111
0.2 total harmonic distortion THD 0.2
0.5
%
0.5
%
signal to noise ratio
S/N
70
75
dB
Mute attenuation I2C-Bus Interface LOW level input voltage for both SDA and SCL HIGH level input voltage for both SDA and SCL Hysteresis of Schmitt trigger inputs
aMUTE
75
90
dB
VIL VIH Vhys
-0.5 3 0.2
1.5 VVD + 0.5
V V V
Pulse width of spikes which must t be suppressed by the input filters SP LOW level output voltage (open collector) VOL1 VOL2 0 0 20 + 0.1Cb -10 0 1.3
50 0.4 0.6 250 10 400
ns V 3 mA sink current 6 mA sink current
Output fall time from VIHmin to VILmax with a bus tOF capacitance from 10 pF to 400 pF Input current for both SDA + SCL Ii SCL clock frequency Bus free time between a STOP and START condition fSCL
ns A kHz s s s s s
tBUF
Hold time (repeated) START condition. After this period, the first tHD,STA clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Set-up time for repeated START condition Data hold time: for I2C-bus devices Data set-up time Rise time of both SDA + SCL
0.6 1.3 0.6 0.6 0 100 20 + 0.1Cb 19 300 0.9
tLOW tHIGH tSU,DAT tHD,DAT tSU,DAT
tR
s ns ns
Semiconductor Group
21.7.99
Data Sheet
Limit Values Parameter Symbol min Fall time of both SDA + SCL Set-up time for STOP condition Capacitive load for each bus line tF tSU,STO Cb 20 + 0.1Cb 0.6 400 typ max 300 ns s pF Unit
TDA6170X
Test conditions
Semiconductor Group
20
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Data Sheet 12 Application Circuit
TDA6170X
Semiconductor Group
21
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Data Sheet 13 Test circuit
TDA6170X
Semiconductor Group
22
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Data Sheet 14 Diagrams
14.1 I2C-Bus Timing
TDA6170X
Semiconductor Group
23
21.7.99

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